The present invention relates to high-speed data interfaces, and more particularly to controlling the duty cycle and skew of input/output signals provided by high-speed data interfaces.
The demand for higher speed data interfaces has increased dramatically in the past few years, and this increase shows no signs of abating. As an example, huge amounts of data must be transferred to/from memory devices to other integrated circuits for such applications as music and video playback, image processing, graphics, and others. Many of these demanding applications run on advanced field programmable gate arrays (FPGAs) such as those developed by Altera Corporation of San Jose, Calif.
New interface techniques, such as Double data rate (DDR) and others, have been developed to support these data rates. In a DDR interface, data is read on each (rising and falling) edge of a strobe or clock signal. Output signals for DDR memory interfaces include a data strobe (DQS) signal that is transmitted along with a group of data (DQ) signals that are captured or received by a receiver on a second interface. Typically, when data is being transmitted from the FPGA (i.e. data is being written), the DQS signal is center aligned with the data signals to ensure accurate receipt of the data; and when the data is received, the DQS signal is edge aligned with the data signals.
Since data is read on each edge of the DQS signal, the timing margins at these interfaces are greatly reduced. For future DDR memory devices that target the 800 Mbs to 1 Gbs data rate ranges, the timing budget left for errors caused by the memory controller becomes quite demanding. This demand places a strict burden on the FPGA transmitting circuitry, and may be compounded by environmental effects on the device during operation. To improve this write timing margin and center alignment of the DQS signal with the data signals, it is important to reduce skew between the signals. Additionally since data is transmitted on each edge of a strobe or clock signal, it is important to reduce skew among both edges of the signals and to control a duty cycle of the signals.
Accordingly, what is needed are circuits, methods, and apparatus that reduce skew among input/output signals, at both edges, and that controls the duty cycle of the input/output signals. For example, what is needed are circuits, methods, and apparatus that reduce skew among the DQ and DQS signals at a data interface, such as a data interface on an FPGA device.